1. Field of the Invention
The present invention relates to a scanning line driving circuit, and more particularly to a shift register circuit which is a constituent of the scanning line driving circuit which is used in an electro-optic device such as an image display device, an image sensor, or the like and consists of only field effect transistors of the same conductivity type.
2. Description of the Background Art
In an image display device (hereinafter, referred to as a “display device”) such as a liquid crystal display, a plurality of pixels are arranged in a matrix in a display panel and a gate line (scanning line) is provided for each row of pixels (pixel line) in the display panel. In a cycle of one horizontal period (1H period) of a display signal, the gate lines are sequentially selected and driven, to update a display image. As a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving the pixel lines, i.e., the gate lines, a shift register may be used, which performs a round of shift operation in one frame period of the display signal.
A shift register as a gate line driving circuit consists of a plurality of cascaded shift register circuits each of which is provided for one pixel line, i.e., one gate line. In this specification, each of a plurality of shift register circuits which constitute a gate line driving circuit is referred to as a “unit shift register”. Specifically, an output terminal of each of the unit shift registers constituting the gate line driving circuit is connected not only to a corresponding gate line but also to an input terminal of the subsequent-stage or post-stage unit shift register.
In order to reduce the number of steps in a manufacturing process for a display device, it is preferable that the shift register used in the gate line driving circuit should be constituted of only field effect transistors of the same conductivity type. For this reason, various types of shift registers constituted of only N-type or P-type field effect transistors and various types of display devices each containing such shift registers have been proposed (e.g., Japanese Patent Application Laid Open Gazette No. 2007-35188 (Patent Documents 1), Japanese Patent Application Laid Open Gazette No. 2006-60225 (Patent Documents 2), Japanese Patent Application Laid Open Gazette No. 2004-157508 (Patent Documents 3), Japanese Patent Application Laid Open Gazette No. 2006-24350 (Patent Documents 4), Japanese Patent Application Laid Open Gazette No. 2004-295126 (Patent Documents 5), Japanese Patent Application Laid Open Gazette No. 2002-133890 (Patent Documents 6), Japanese Patent Application Laid Open Gazette No. 2007-250052 (Patent Documents 7), Japanese Patent Application Laid Open Gazette No. 2006-277860 (FIGS. 1, 2, and 3) (Patent Documents 8), Japanese Patent Application Laid Open Gazette No. 2004-246358 (FIG. 1) (Patent Documents 9), and Japanese Patent Application Laid Open Gazette No. 2006-344306 (FIG. 11) (Patent Documents 10)).
FIG. 6 of Patent Documents 1 is a circuit diagram showing a background-art unit shift register constituted of only PMOS transistors. An output signal (OUT) of the unit shift register is activated when a clock signal (C1) is supplied to an output terminal through a transistor (T2) (hereinafter, referred to as a “pull-up transistor”) which brings an output into an active level (L (Low) level herein). High driving capability (capability of carrying current) is required of the pull-up transistor, particularly, since a unit shift register used in a gate line driving circuit drives a gate line which is a large load capacitance by using an output signal. For this reason, an on-state resistance of the pull-up transistor is set very low.
In a normal operation (operation of shifting a signal) of the unit shift register, the pull-up transistors of all the stages are sequentially turned on so that respective output signals of a plurality of cascaded unit shift registers may be sequentially activated. In a state where the potentials of the nodes in the circuit are unsteady, such as immediately after power-on, however, the pull-up transistors of the plurality of unit shift registers are in an ON state in some cases. At that time, if the clock signal is activated, excessive current undesirably flows through the plurality of pull-up transistors of which the on-state resistances are low.
Against the above problem, a countermeasure is taken in the unit shift register shown in FIG. 6 of Patent Documents 1. Specifically, in the unit shift register, a transistor (T7a) (hereinafter, referred to as an “initializing transistor”) which is controlled by an initialization signal (SHUT) is connected between a gate of the pull-up transistor and a power supply (VDD) of inactive level (H (High) level herein). Before the normal operation, the initializing transistors of all the unit shift registers are thereby turned on temporarily by using the initialization signal. In all the unit shift registers, gate potentials of the pull-up transistors are thereby initialized to an inactive level, to get out of the unsteady state. As a result, since all the pull-up transistors are turned off, even if the clock signal is activated, no excessive current flows through the plurality of pull-up transistors.
In the unit shift register shown in FIG. 6 of Patent Documents 1, however, providing the initializing transistor (T7a) causes another problem. Hereafter, this problem will be discussed.
In the unit shift register, when the output signal (OUT) is activated, the gate potential of the pull-up transistor (T2) is lowered by coupling through a gate-channel capacitance (MOS capacitance) of the pull-up transistor. Since an absolute value of a gate-source voltage of the pull-up transistor is thereby maintained large, the on-state resistance of the pull-up transistor can be maintained low and it is possible to prevent a decrease in the rate of change of the output signal to the active level (fall of the output signal herein). This effect is increased as the fall range of the gate potential of the pull-up transistor becomes larger. Since the fall range depends on a ratio between the MOS capacitance of the pull-up transistor and a parasitic capacitance of a node (n2) connected to the gate, it is preferable that the parasitic capacitance of the node connected to the gate of the pull-up transistor should be smaller.
Since the above-described initializing transistor (T7a) is connected to the gate of the pull-up transistor in the unit shift register, however, the parasitic capacitance of the node connected to the gate of the pull-up transistor becomes larger by a drain-gate capacitance of the initializing transistor. As a result, if the gate potential of the pull-up transistor does not sufficiently fall when the output signal is activated, there arises a problem that the driving capability of the pull-up transistor decreases and the falling rate of the output signal decreases.
Further, in a case where the initialization signal (SHUT) is externally inputted, like in the unit shift register shown in FIG. 6 of Patent Documents 1, it is necessary to provide a circuit for generating the initialization signal as an external circuit and this causes an increase of the manufacturing cost.